1. Field of the Invention
The present invention relates to a multi-value single electron memory using a multi-quantum dot, in which a floating gate (FG) of a EEPROM or a flash memory is formed of two quantum dots, and the two quantum dots are applied to multi-value memories, and a driving method thereof.
2. Description of the Related Art
Floating gate (FG)-type flash memories, which are existing memories using single electron charging, have been studied by many researchers. Hitachi introduced a 128M SET flash memory which operates at room temperature (U.S. Pat. No. 5,600,163) at academic society early in 1998. IBM has U.S. Pat. Nos. 5,714,766 and 5,801,401 wherein an enormous number of nano crystals are formed on an existing FET channel, and the resultant structure is applied to a floating gate (FG). Fujitsu in U.S. Pat. No. 5,886,380 and Minnesota University in WO Pat. No. 9,905,724 introduced a non-volatile memory which operates at room temperature using the principle that a single electron can screen a channel by forming a nanometer-sized quantum dot on an FET channel and applying the quantum dot to an FG and setting the width of a channel to be smaller than the Debye screen length (LD) of an electron. NEC in Appl.Phys.Lett Vol 71, p 2038, 1997, and NTT in Electron.Lett, Vol 34, p 45, 1998 introduced a memory which operates a single electron transistor as an electrometer which indirectly detects the presence of electrons to a precision of a single electron and thus determines whether electrons are stored in a floating gate (FG). However, the SET flash memory of Hitachi has critical drawbacks in that the operating voltage is very high, and nano crystals used for a floating gate and nano crystals applied as a channel cannot be arbitrarily controlled in contrast to other memories. The memory introduced by IBM causes fluctuations in xcex94Vth and temperature due to the difficulty in maintaining the sizes of nano crystals, which are applied as a floating gate, to be uniform. The basic concept of the memories introduced by Fujitsu and Minnesota University is realization of a flash SET memory using the effect of charging with a single electron by making the width of a channel equal to or smaller than the Debye screen length. However, the memories introduced by Fujitsu and Minnesota University have problems in that the retention time is less than 5 seconds since recording by direct tunneling increases leakage current. In order to increase the retention time, the thickness of a dielectric film SiO2 used as a tunneling barrier must be increased, and accordingly, a writing method must be changed. Also, about 20 electrons other than one electron must be charged in a floating gate (FG). The memories introduced by Fujitsu and Minnesota University use one quantum dot. When the channel length is reduced to achieve high integration, the memories are subjected to short channel effect (SCE) due to the scale down of a general MOSFET, which makes ultra-high integration difficult. In particular, reproducible and uniform control of a floating gate to have a size of several manometers cannot be secured, and fluctuations in xcex94Vth are caused by the difficulty in accurately controlling the number of electrons with which a floating gate (FG) is charged. In the memories produced by NEC and NTT, the structure of elements and a fabrication process thereof are very complicated.
According to the results of analysis made on the characteristics and realizability of the memory devices to which the above-identified patent are directed a method of forming a floating gate of numerous nano crystals, which is proposed by IBM, that is, constitution of one bit using more than several tens of electrons, was estimated to provide excellent reliability. However, as set forth above, the memory proposed by IBM also cannot arbitrarily control the number of nano crystals, so that the memory proposed by Fujitsu and Minnesota University, which can arbitrarily control the number of nano crystals and applies one quantum dot, can be more preferable to the memory of IBM if several drawbacks are solved.
To solve the above problems, an objective of the present invention is to provide a multi-value single electron memory using a double quantum dot, in which the width of a channel is made smaller than a Debye screen length by controlling the impurity concentration of a substrate so that a single electron can artificially screen a channel, a multi-value function is provided by arranging two quantum dots on a source and a drain to overcome a limit in ultrahigh integration due to short channel effect (SCE), a writing technique is changed to a channel hot electron injection (CHEI) technique, and a memory capacity of 1 Tb or greater is obtained by charging quantum dots with different numbers of several tens of electrons, and a driving method thereof.
To achieve the above objective, the present invention provides a multi-value single electron memory using a double quantum dot, including: a channel region having a width which is equal to or less than the Debye screen length, on a semiconductor substrate; a source and a drain doped with different impurities to the impurities of the channel region, the source and the drain formed having the channel region between them; an insulating layer formed on the source, the drain and the channel region; first and second floating gates formed in the insulating layer on the source and the drain on both ends of the channel region to act as quantum dots; and a control gate formed on the insulating layer which covers the first and second floating gates.
In the present invention, the semiconductor substrate is a silicon substrate doped at a concentration of 1018xe2x88x921013/cm3, and the two floating gates, which act as quantum dots, stores different amounts of electrons using a channel hot electron injection (CHEI) technique, and thus provides multi-value storage functions depending on the number of electrons stored in each quantum dot. The two floating gates can be charged with different amounts of electrons by applying a positive voltage amount to one of the source and drain and an identical negative voltage amount to the other and making the charge capacities of the floating gates different. Alternatively, the two floating gates can be charged with different amounts of electrons by applying a positive voltage amount to one of the source and drain and a different negative voltage amount to the other while equalizing the sizes of the floating gates.
Preferably, the width of the channel is set to be equal to or less than the Debye screen length which is determined by the concentration of impurities doped in the silicon substrate, so that a threshold voltage fluctuation in the channel is caused by charging with one electron.
Also, in the present invention, the insulating film is formed by depositing SiO2, Al2O3, AlN, AlON or SiON to a thickness of 100 nm or less, and acts as a tunnel barrier. Alternatively, the insulating film is formed by depositing TiO2/SiO2, Ta2O5/SiO2, SiON/SiO2, AlON/SiO2, AlN/SiO2, or Al2O3/SiO2 to a thickness of 100 nm or less, and acts as a tunnel barrier. Each of the first and second floating gates has a width which is equal to or smaller than the width of the channel, a thickness of 100nm or less, and a diameter of 10 nm or less. Furthermore, it is preferable that the width, thickness and diameter of the first and second floating gates are reduced due to electric field oxidation, and both ends of each of the quantum dots are shaped of a bird beak. The first and second floating gates are doped with n-type impurities using an implanter or a diffusion furnace. The insulating layer on the first and second floating gates is formed of SiO2, Al2O3, AlN, AlON, SiON, TiO2/SiO2, Ta2O5/SiO2, SiON/SiO2, AlON/SiO2, AlN/SiO2, or Al2O3/Si2 to a thickness of 100 nm or less. Preferably, the control gate is formed of at least one material selected from the group consisting of Al, W, Co, Ti and polysilicon. Here, a polysilicon control gate is doped with n-type impurities using an implanter or a diffusion furnace.
In order to achieve the above objective, the present invention provides another multi-value single electron memory using a double quantum dot, including: a channel region having a width which is equal to or less than the Debye screen length, on a semiconductor substrate; a source and a drain doped with different impurities to the impurities of the channel region, the source and the drain formed having the channel region between them; an insulating layer formed on the source, the drain and the channel region; first and second floating gates formed in the insulating layer on the source and the drain on both ends of the channel region to act as quantum dots; and a control gate formed on the insulating layer which covers the first and second floating gates, wherein memory cells are arrayed on the semiconductor substrate in a matrix, the control gates are arrayed in strips to form word lines, and the drain is connected to bit lines which arrayed in strips so as to cross the word lines.
In the present invention, the semiconductor substrate is a silicon substrate doped at a concentration of 1018xe2x88x921013/cm3, and the two floating gates, which act as quantum dots, store different amounts of less than several tens of electrons and thus provide multi-value storage functions depending on the number of electrons stored in each quantum dot. Preferably, the width of the channel is set to be equal to or less than the Debye screen length which is determined by the concentration of impurities doped in the silicon substrate, so that a threshold voltage fluctuation in the channel is caused by charging with one electron.
Also, in the present invention, the insulating film is formed by depositing SiO2, Al2O3, AlN, AlON or SiON to a thickness of 100 nm or less, and acts as a tunnel barrier. Alternatively, the insulating film is formed by depositing TiO2/SiO2, Ta2O,/SiO2, SiON/SiO2, AlON/SiO2, AlN/SiO2, or Al2O3/SiO2 to a thickness of 100 nm or less, and acts as a tunnel barrier. Each of the first and second floating gates has a width which is equal to or smaller than the width of the channel, a thickness of 100 nm or less, and a diameter of 10 nm or less. Furthermore, it is preferable that the width, thickness and diameter of the first and second floating gates are reduced due to electric field oxidation, and both ends of each of the quantum dots are shaped of a bird beak. Also, preferably, the first and second floating gates are doped with n-type impurities using an implanter or a diffusion furnace, and the insulating layer on the first and second floating gates is formed of SiO2, Al2O3, AlN, AlON, SiON, TiO2/SiO2, Ta2O/SiO2, SiON/SiO2, AlON/SiO2, AlN/SiO2, or Al2O3/SiO2 to a thickness of 100 nm or less. It is preferable that the control gate is formed of at least one material selected from the group consisting of Al, W, Co, Ti and polysilicon. Here, a polysilicon control gate is doped with n-type impurities using an implanter or a diffusion furnace.
To achieve the above objective, the present invention provides a method of driving a multi-value single electron memory using a double quantum dot, the memory including: a channel region having a width which is equal to or less than the Debye screen length, on a semiconductor substrate; a source and a drain doped with different impurities to the impurities of the channel region, the source and the drain formed having the channel region between them; an insulating layer formed on the source, the drain and the channel region; first and second floating gates formed in the insulating layer on the source and the drain on both ends of the channel region to act as quantum dots; and a control gate formed on the insulating layer which covers the first and second floating gates, wherein memory cells are arrayed on the semiconductor substrate in a matrix, the control gates are arrayed in strips to form word lines, and the drain is connected to bit lines which arrayed in strips so as to cross the word lines. This method includes performing writing by charging the second floating gate FG2 with a predetermined number of electrons in consideration of a channel hot electron injection (CHEI) technique by applying a source-drain voltage Vds of less than 12 Volts and a control gate voltage Vg of less than 15 Volts to a selected memory cell, or by charging another selected memory cell with a different number of electrons to the number of electrons charged in the second floating gate by applying a source-drain voltage Vds of less than xe2x88x9212 Volts and a control gate voltage Vg of less than 15 Volts to the other selected memory cell. Also, this method includes performing erasing by slipping the electrons charged in the writing step from the second floating gate and going into the control gate by opening the source-drain voltage Vds and applying a control gate voltage Vg of about 15 Volts to the second floating gate, using a Fowler-Nordheim (F-N) tunneling method. Furthermore, the method includes reading written information by detecting current values of the selected cells by applying a drain-source voltage Vds of less than 5 Volts to a cell selected to read out, and applying the middle value of the threshold voltage Vth of the first floating gate FG1 and the threshold voltage Vth of the second floating gate FG2 selected as a control gate voltage Vg to the selected cell.